Blue Pearl Software
Blue Pearl provides products that automate manual, error prone processes at the functional design stage for FPGA and ASIC. We validate that design specifications are met at the register transfer level (RTL) so that downstream tools in the chip design flow have the directives needed to synthesize and implement the design.
Analyze RTL™ checks functional design integrity and conformance to rules and methodology.
Blue Pearl CDC identifies clock domain crossing (CDC) issues and use various techniques such as Grey Cell methodologies to solve these critical issues.
HDL Creator is a smart editor ideal for developers coding both RTL and test benches. HDL Creator provides real-time syntax and style code checking inside an intuitive, easy-to-use full featured editor with advanced design views to help understand, debug and verify as you code.
The Blue Pearl Management Dashboard delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality.
Blue Pearl’s innovative technology tools accelerate design implementation and improve product quality by enabling fixes to issues early, when they are easiest and quickest to fix, so lowering the overall simulations and design cost and making the design process more predictable.